Verilog FPGA design for generating wavetrain with variable ON time , but constant OFF time (Byte to wavetrain coding)

2018-07-10 10:31:35

This is for a project that I'm working on, which uses FPGA (INTEL ALTERA MAX 10) as an interface between 2 systems.

I need to write vhdl/verilog code for generating wavetrain with variable ON time , but constant OFF time.

Why? Because, I need to convert a byte into a waveform. High bit represents, 100us OFF time and 200us ON time. and likewise, low bit represent, 100us off time and 100us ON time.

So, for example, 1001 will be represented by, LOW(100us)->HIGH(200us)->LOW(100us)->HIGH(100us)->LOW(100us)->HIGH(100us)->LOW(100us)->HIGH(200us)

Please help me out as I'm a computer science graduate and I'm not very familiar with HDL languages. Other systems involved in this project does not involve HDL, but just this FPGA based interfacing does.

Will be highly obliged if I can get any help in solving this.

Thanks in advance.